Documentation and Looking at UDP core

Part of good working habit is to document every thing. I have seen it and i believe it is extremely useful. So read the Spec


 As i am done with RTP golden model, i am about to write RTP Verilog model. I was figuring out myself as well as with my mentor what would the interface to UDP core look like.There are two possibilities

1)Assume there is downstream UDP core to begin with that accepts data.In this case, interface is easy as you can see how UDP accepts data.

2) If no UDP core or UDP core does not have interface to accept data, then you can add UDP header on the same spot where you are inserting RTP header. Not only that, you can also insert IP header as well. That means now you have to interface RTP with the MAC core.

The two cores i looked at are

http://www.joelw.id.au/FPGA/DigilentAtlysResources

This falls in the 2nd category

and

http://opencores.org/project,udp_ip_stack

which is sadly down throughout today and i could n't figure out if it belongs to 1st of 2nd category. I will try again tomorrow.