RTP Verilog Code and Synthesis

Today was getting hands dirty writing Verilog code. The interface of the RTP core is shown in Figure 6 of Specification. Note that RTP core will add UDP/IP and Ethernet Headers as well in the near future. The code correctly generates RTP packet i.e., header and payload (chosen to be small enough to debug).The design has also gone through synthesis Xilinx Synthesis flow and successfully post-synthesis simulation. The code is available on bitbucket. The RTL file for RTP is packetizer.v, the testbench is tb_packetizer.v. The post-synthesis netlist is packetizer_synthesis.v. You need Xilinx unisims, simprims, uni9000 and unimacro libraries to run the post-synthesis simulation.

Here is a brief log of the RTL Run. If you have read the Specification (in particular pages 3-4), this should make sense

                  0: 0000000000000000000000000000000000000000000000000000000000

                 145: 80180000000000000000000000000500001a0000000007000008000009

                 195: 80180001000000000000000000000500001a050000000a00000b00000c

                 245: 80180002000000000000000000000500001a0a0000000d00000e00000f

                 295: 80180003000000000000000000000500001b0000000010000011000012

                 345: 80180004000000000000000000000500001b0500000013000014000015

                 395: 80180005000000000000000000000500001b0a00000016000017000018

                 445: 80180006000000000000000000000500001c000000001900001a00001b

                 495: 80180007000000000000000000000500001c050000001c00001d00001e

  Here is a snapshot of the RTL simulation

Here is a brief log of the post-synthesis simulation

                   0: 0000000000000000000000000000000000000000000000000000000000

                 145: 80180000000000000000000000000500001a0000000007000008000009

                 195: 80180001000000000000000000000500001a050000000a00000b00000c

                 245: 80180002000000000000000000000500001a0a0000000d00000e00000f

                 295: 80180003000000000000000000000500001b0000000010000011000012

                 345: 80180004000000000000000000000500001b0500000013000014000015

                 395: 80180005000000000000000000000500001b0a00000016000017000018

                 445: 80180006000000000000000000000500001c000000001900001a00001b

                 495: 80180007000000000000000000000500001c050000001c00001d00001e

                 545: 80180008000000000000000000000500001c0a0000001f000020000021

                 595: 80180009000000000000000000000500001d0000000022000023000024

Here is a snapshot of the post-synthesis simulation

The Synthesis summary report is packetizer.syr

As the code is uploaded to bitbucket, please help test it. Thanks in advance