Implementing XAPP 495 on Spartan 6

Today, i decided to do hardware testing and chose to implement the VTC reference design given in http://bit.ly/1lluJn1 on Atlys board. I was able to implement the design successfully on Atlys board.

Here are a few snapshots of the 720p frame

Not only that, i was able to capture this HDMI traffic for the purpose of using it as RTP payload. I shall add the Verilog files that capture the HDMI to the bitbucket tomorrow. Here is a snapshot of the captured HDMI traffic going from FPGA to the monitor.

                 720p resolution chosen

                 512: en=1,hsync=1,vsync=1,red= 0,green= 0,blue= 0

                 525: en=1,hsync=0,vsync=0,red= 0,green= 0,blue= 0

                 539: en=1,hsync=0,vsync=0,red= 0,green= 0,blue= 0

                 553: en=1,hsync=0,vsync=0,red= 0,green= 0,blue= 0

                 566: en=1,hsync=0,vsync=0,red= 0,green= 0,blue= 0

                 580: en=1,hsync=0,vsync=0,red= 0,green= 0,blue= 0

                 593: en=1,hsync=0,vsync=0,red= 0,green= 0,blue= 0

                 607: en=1,hsync=0,vsync=0,red= 0,green= 0,blue= 0

                 620: en=1,hsync=0,vsync=0,red= 0,green= 0,blue= 0

                 634: en=1,hsync=0,vsync=0,red= 0,green= 0,blue= 0

                 647: en=1,hsync=0,vsync=0,red= 0,green= 0,blue= 0

                 661: en=1,hsync=0,vsync=0,red= 0,green= 0,blue= 0

                                .

                                .

                                .

HSync and VSync signals shall also be added to the packetizer upstream interface.