Now the plan is to work on the weekend to complete the 40 hours as well as next week during which i am suppose to be on vacation.
I had taken GSoC on my nerves. That is why my sleep and work cycle got unbalanced this week. I want to unwind myself and today (Friday) i focused on that. My goal is to complete the project and enjoy the experience rather than hosed.
Anyway, got MyHDL 0.9-dev working. Now i can pass interfaces. I was able to run the code passed to me by Chris. The code treats Image buffer FIFO as shown in Figure 2 of the Spec
https://docs.google.com/document/d/1PSjfm6eS0B3UUPJmPf7PH0tNsF7ZFKIKfPldmF3ucKY/edit
Tomorrow (Saturday May 31st), integration of simulation models of Image Buffer -> RTP -> UDP in MyHDL will be dealt with.
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