Here is the GTK waveform.
Thursday, May 22, 2014
Defining FIFO Upstream Interface using MyHDL Python library for Hardware Design
Today was learning MyHDL and putting into practice. My mentor created an exercise based on HDMI2Ethernet Specfication. Note that this specification is still in progress.The exercise objective is to mimic HDMI2USB' FIFO upstream interface. Once this interface is correctly implemented in hardware and and tested by testbench + waveform viewer, we can proceed downstream towards Blocks that need to be implemented for this project like RTP packet processing, UDP packet processing, IP packet processing, and Ethernet packet processing. All the Files are available to download from my bitbucket.
Here is the GTK waveform.
Here is the GTK waveform.
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Glad to see the simulation! But the simulation does not include the full bus specification you outlined in figure 2 in the in progress specification. Work on having the complete interface that aligns exactly with the raw video stream in the HDMI2USB.
ReplyDeleteWhat you want to do, as a first step, is define the interfaces into the module you are developing and then create simulation models to drive the interfaces. For now, the module you are developing will be an empty stub. We want to have the ability to stimulate and monitor the module under development. I sent you a diagram that defines the simulation models and the HDL modules that you need to define for a verification environment.
Hi Chris,
ReplyDeleteI have added the downstream interface as well to the bitbucket. I hope this is what you are looking for. Please continue to post if there are any questions or comments.
Thanks a lot