FIFO Downstream Interfacing using MyHDL

Today the objective was to define the FIFO downstream interface as defined in the HDMI2Ethernet Specification document that will interface with the RTP block. I also cleaned up the source code tree on Bitbucket. It should look more cleaner with README.txt and conversion directory that holds the Verilog and VHDL modules. Figure 1 shows the Simulation waveform

Figure 1: FIFO downstream interface capture waveform

The objective of yesterday's and today's exercise is to create simulation models (flexible models that can leverage full features of Python as these blocks don't need to be converted to Hardware (Verilog or VHDL) ) as many as necessary in HDMI2Ethernet Pipeline shown in Blue in Figure 2. The yellow Block such as Packetizer needs to be converted to Hardware and thus needs a strict HDL (Verilog or VHDL) modeling. This will become clear in the forthcoming weeks.

Figure 2: Design and Verification environment

Looking forward to Memorial day long weekend !!!