FPGA Hello World

Got the Stroby working!!!. Here is the demo.

The updated files can be found on my bitbucket

Now Working on models for simulation and verification of HDMI2Ethernet pipeline as shown in the Figure below. Blue blocks show simulation models. Yellow Blocks show hardware models

Figure 1: HDM2Ethernet Simulation and Verification flow

The idea is first create accurate golden model for hardware blocks. This is to make sure RTP packets are generated, encapsulated as UDP packets, UDP gets encapsulated as IP packets and IP packets are encapsulated as Ethernet packets.

The goal of this week is to create golden model for packetizer and test it together with upstream and downstream blocks.