Opening the Xilinx Atlys Board

Items that i want to cover today

• Opening the FPGA Box
• Python Scapy
• HDMI2Ethernet Pipeline

I am aiming to try MyHDL FPGA Tutorial I (LED Strobe) on my Xilinx Atlys Board

I found that it has 100 MHz input clock from Xilinx Atlys Board Reference Manual

The above MyHDL tutorial is little bit hard to follow.So i ended up creating my own version. Once i got the led strobe working in Python. The next step was to convert it to Verilog and then go through the entire Xilinx Build Flow till bit file generation. I got the Verilog conversion correctly. Unfortunately, the provided compile_stroby.py does not work to generate bit file from Verilog. I will report it to the author of the tutorial.So, I took the other route. I manually created Xilinx ISE project for Atlys Spartan 6 board (XC6SLX45), imported Verilog file, manually created constraint file (my_stroby.ucf) and clicked the Implementation flow. As a result, i got the bit file generated. I was able to program the board successfully using Xilinx Impact. Unfortunately, the leds are not blinking, despite spending almost 2 hours (its 1:44 AM now :(  )

I will debug it in the morning.

The files can be found on my bitbucket

Today was the last holiday from long weekend but i thought to do something to keep going.