If you recall, last week, packets sent by Packetizer were getting dropped or were missing. It turned out that 1 Gbps MAC that is integrated with Packetizer was overflowing despite making sure all flow control protocols were followed while interfacing with the MAC. To deal with this, delay was inserted between each RTP packet so MAC never overruns. It fixed everything and you could see entire RED frame, RGB flag and RGB loop. The only thing that got hurt is the frame per second.
So i am trying to figure out how to debug this MAC and get the fps up. I shall see if i could post some calculations of the current implementation.
Happy Debugging.
Tariq,
ReplyDeleteNot sure if you are simulating with the Eth MAC or not. I have
a verificaiton environment of the MAC that you might be able to
use to help debug.
I have put together a cosimulation of the Ethernet MAC you are
using, and you can easily interface your packetizer. But it will
take a little work and this is very different approach than the
straightforward Verilog or VHDL verification methods ... not sure
if it would be more of a distraction or a help.
The verification environment is fairly raw, the good thing, you
will have lots of tools to work from high-level (working with
images and higher-level packet types). This similar to the
approach we started at the beginning of the project.
I have the simulation environment in the same place were we had
the models from before:
https://bitbucket.org/cfelton/gsoc/src/tip/2014/examples/simple_gemac_core/test/?at=default
If you want to try and utilize this for debug let me know, I have
replace the Xilix coregen FIFOs with my own, you don't need to
bother with their POS tools and crappy sim files. Take note, this
isn't a quick solution. It will probalby take a little time to
get running but when you do you will have unlimited visibility.
Regards,
Chris