Debugging continues and eventually pays off: One RTP packet swims across the wire

All the timing violations are corrected. The build flow works great. But wireshark is not capturing anything. The whole day was dedicated to debugging why packets are not coming out of FPGA.
This will continue until problem solved. I am going to upload the design and log files later so you may suggest.

I am thinking of putting a testbench and check the simulation after each of the synthesis, translation, mapping and p&r phases.

The other would be to use Chipscope.

Debug mode continues.

And finally the good news, one RTP packet made it across the English channel ( i mean the Ethernet wire).

Here is the snapshot. Note that RTP is sent as UDP packet. Only Look at the first packet.

Now i will send more RTP packets and work backwards towards putting a DDR2 or similar and connecting that with VTC_DEMO colorbar.