Today, i generated montonically incrementing RGB values as part of the packetizer and send that to the MAC after adding all the headers like RTP, UDP, IP and Ethernet. The simulation worked just fine. After that it was time to do the Xilinx build flow to make the RTP go across the 1 Gbps network. It took more than an hour to get the build flow finish. And lo and behold, i was struck by timing violations. Time to fix this by re-coding.
Debug mode continues
How are you interfacing with the "simple_gemac". If you are interfacing to the "simple_gemac_wrapper" and the tx_f36_* FIFO interface you don't need to use the 125 MHz clock on the FIFO side, you can use a lower clock rate (GTX_CLK/4).
ReplyDeleteRegards,
Chris