Thursday, July 17, 2014

Debugging Verilog RTP Packetizer frame generation

Packetizer Verilog RTL is somehow missing some packets when i . This was reported in the day before yesterday's blog. I am still trying to debug it. I might go with simulation or chipscope approach. Right now i am making changes and testing in the hardware.

I also posted the instructions on how to reproduce yesterday's blog results of sending one row of 1280 pixels by FPGA and reconstruction in Gstreamer. Please look at the README.md

Debugging will continue on the weekend or next week as i have some commitment on Friday July 18th. See you after a short break !
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1 comment:

  1. Christopher FeltonJuly 18, 2014 at 6:57 AM

    Tariq, thanks for the directions. I will follow the directions tonight and give you feedback.

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